VPSHUFLW
REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b
x86_64 X86_LEGACY AVX512 AVX2 source: xed
XED_VPSHUFLW_X86_LEGACY_ONEBYTE_70_33961
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 70 70 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 1 |
| imm_size_bytes | 1 |
| exception_class | avx-type-4 |
| cpl | 3 |
| raw_encoding | VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | MEM0 | MEM | R | EXPLICIT | MODRM_RM | ||
| 2 | IMM0 | IMM | b | R | EXPLICIT | IMM | |
| 3 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 5 | IMM1 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.