VPSLLDQ
AVX512 AVX512BW_128 x86_64
VPSLLDQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 8 encoding forms, distinguished by opcode byte: 73.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPSLLDQ_X86_LEGACY_ONEBYTE_73_266148
REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b
XED_VPSLLDQ_X86_LEGACY_ONEBYTE_73_855021
REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b
XED_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512
REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b
XED_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512
REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b
XED_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512
REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b
XED_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512
REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b
XED_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512
REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b
XED_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512
REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b