VPSRAQ
AVX512 AVX512F_128 x86_64
12 encoding forms.
XED_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
XED_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
XED_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
XED_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
XED_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
XED_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
XED_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
XED_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
XED_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
XED_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
XED_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
XED_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64