VPSRAVD

REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq

x86_64 X86_LEGACY AVX512 AVX2 source: xed

XED_VPSRAVD_X86_LEGACY_ONEBYTE_46_25917

Encoding

encoding_kindX86_LEGACY
opcode_bytes46 46 46 46
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l1
exception_classavx-type-4
cpl3
raw_encodingVV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0

Operands (12)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG R EXPLICIT MODRM_REG
2 MEM0 MEM R EXPLICIT MODRM_RM
3 REG2 REG w W EXPLICIT MODRM_REG
4 REG3 REG R EXPLICIT MODRM_REG
5 REG4 REG R EXPLICIT MODRM_REG
6 REG5 REG w W EXPLICIT MODRM_REG
7 REG6 REG R EXPLICIT MODRM_REG
8 MEM1 MEM R EXPLICIT MODRM_RM
9 REG7 REG w W EXPLICIT MODRM_REG
10 REG8 REG R EXPLICIT MODRM_REG
11 REG9 REG R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.