VPSRLD

XED_VPSRLD_X86_LEGACY_ONEBYTE_72_58946

REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b

X86_LEGACY 72 /2 AVX

XED_VPSRLD_X86_LEGACY_ONEBYTE_72_838472

REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b

X86_LEGACY 72 /2 AVX2

XED_VPSRLD_X86_LEGACY_ONEBYTE_D2_639848

REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64

X86_LEGACY D2 D2 /r AVX2

XED_VPSRLD_X86_LEGACY_ONEBYTE_D2_916927

REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64

X86_LEGACY D2 D2 /r AVX

XED_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512

REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b

X86_LEGACY 72 /2 AVX512F_128

XED_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512

REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b

X86_LEGACY 72 /2 AVX512F_128

XED_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512

REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32

X86_LEGACY D2 /r AVX512F_128

XED_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512

REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32

X86_LEGACY D2 /r AVX512F_128

XED_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512

REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b

X86_LEGACY 72 /2 AVX512F_256

XED_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512

REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b

X86_LEGACY 72 /2 AVX512F_256

XED_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512

REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32

X86_LEGACY D2 /r AVX512F_256

XED_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512

REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32

X86_LEGACY D2 /r AVX512F_256

XED_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512

REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b

X86_LEGACY 72 /2 AVX512F_512

XED_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512

REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b

X86_LEGACY 72 /2 AVX512F_512

XED_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512

REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32

X86_LEGACY D2 /r AVX512F_512

XED_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512

REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32

X86_LEGACY D2 /r AVX512F_512