VPSRLVQ

AVX512 AVX512F_128 x86_64

7 encoding forms.

XED_VPSRLVQ_X86_LEGACY_ONEBYTE_45_67137
REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq
X86_LEGACY 45 45 45 45 /r AVX2
XED_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 45 /r AVX512F_128
XED_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
X86_LEGACY 45 /r AVX512F_128
XED_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 45 /r AVX512F_256
XED_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
X86_LEGACY 45 /r AVX512F_256
XED_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
X86_LEGACY 45 /r AVX512F_512
XED_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64
X86_LEGACY 45 /r AVX512F_512