VPTESTNMD
LOGICAL AVX512F_128 x86_64
6 encoding forms.
XED_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32
XED_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32
XED_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR
XED_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32