VREDUCEBF16
AVX512 AVX10_2_BF16_128 x86_64
6 encoding forms.
XED_VREDUCEBF16_XMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
XED_VREDUCEBF16_XMMbf16_MASKmskw_XMMbf16_IMM8_AVX512
REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:bf16 IMM0:r:b
XED_VREDUCEBF16_YMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
XED_VREDUCEBF16_YMMbf16_MASKmskw_YMMbf16_IMM8_AVX512
REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:bf16 IMM0:r:b
XED_VREDUCEBF16_ZMMbf16_MASKmskw_MEMbf16_IMM8_AVX512
REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:bf16:TXT=BCASTSTR IMM0:r:b
XED_VREDUCEBF16_ZMMbf16_MASKmskw_ZMMbf16_IMM8_AVX512
REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zbf16 IMM0:r:b