VREDUCEPS
AVX512 AVX512DQ_128 x86_64
VREDUCEPS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 6 encoding forms, distinguished by opcode byte: 56.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
XED_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b
XED_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
XED_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b
XED_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
XED_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b