VRSQRT28SS

AVX512 AVX512ER_SCALAR x86_64

VRSQRT28SS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 2 encoding forms, distinguished by opcode byte: CD.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

XED_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32
X86_LEGACY CD /r AVX512ER_SCALAR
XED_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32
X86_LEGACY CD /r AVX512ER_SCALAR