VSM4RNDS4
AVX512 SM4_128 x86_64
10 encoding forms.
XED_VSM4RNDS4_XMMu32_XMMu32_MEMu32
REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32
XED_VSM4RNDS4_XMMu32_XMMu32_MEMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:dq:u32
XED_VSM4RNDS4_XMMu32_XMMu32_XMMu32
REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32
XED_VSM4RNDS4_XMMu32_XMMu32_XMMu32_AVX512
REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32
XED_VSM4RNDS4_YMMu32_YMMu32_MEMu32
REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32
XED_VSM4RNDS4_YMMu32_YMMu32_MEMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=YMM_N3():r:qq:u32 MEM0:r:qq:u32
XED_VSM4RNDS4_YMMu32_YMMu32_YMMu32
REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32
XED_VSM4RNDS4_YMMu32_YMMu32_YMMu32_AVX512
REG0=YMM_R3():w:qq:u32 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32
XED_VSM4RNDS4_ZMMu32_ZMMu32_MEMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=ZMM_N3():r:zu32 MEM0:r:zd:u32
XED_VSM4RNDS4_ZMMu32_ZMMu32_ZMMu32_AVX512
REG0=ZMM_R3():w:zu32 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32