ADCX
REG0=GPR32_N():w:d:i32 REG1=GPR32_R():r:d:i32 REG2=GPR32_B():r:d:i32
x86_64 X86_LEGACY APX APX_F_ADX_N3 source: xed
XED_ADCX_GPR32i32_GPR32i32_GPR32i32_APX_N3
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 00 |
| opcode_map | ONEBYTE |
| mandatory_prefix | 66 |
| has_modrm | True |
| vex_l | 0 |
| requires_mode | long |
| attributes | APX_NDD |
| exception_class | APX-EVEX-INT |
| cpl | 3 |
| raw_encoding | EVV 0x66 V66 MAP4 MOD[0b11] MOD=3 UBIT=1 REG[rrr] RM[nnn] ND=1 NF=0 W0 VL128 mode64 ZEROING=0 EVAPX() |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | d | R | EXPLICIT | MODRM_REG | |
| 2 | REG2 | REG | d | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.