ADCX
APX APX_F_ADX x86_64
ADCX is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category APX. This page lists its 10 encoding forms, distinguished by opcode bytes: 00, 0F, 38, F6.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_ADCX_X86_LEGACY_0F38_F6_315698
ry, ry/my
XED_ADCX_GPR32i32_GPR32i32_APX
REG0=GPR32_R():rw:d:i32 REG1=GPR32_B():r:d:i32
XED_ADCX_GPR32i32_GPR32i32_GPR32i32_APX_N3
REG0=GPR32_N():w:d:i32 REG1=GPR32_R():r:d:i32 REG2=GPR32_B():r:d:i32
XED_ADCX_GPR32i32_GPR32i32_MEMi32_APX_N3
REG0=GPR32_N():w:d:i32 REG1=GPR32_R():r:d:i32 MEM0:r:d:i32
XED_ADCX_GPR32i32_MEMi32_APX
REG0=GPR32_R():rw:d:i32 MEM0:r:d:i32
XED_ADCX_GPR64i64_GPR64i64_APX
REG0=GPR64_R():rw:q:i64 REG1=GPR64_B():r:q:i64
XED_ADCX_GPR64i64_GPR64i64_GPR64i64_APX_N3
REG0=GPR64_N():w:q:i64 REG1=GPR64_R():r:q:i64 REG2=GPR64_B():r:q:i64
XED_ADCX_GPR64i64_GPR64i64_MEMi64_APX_N3
REG0=GPR64_N():w:q:i64 REG1=GPR64_R():r:q:i64 MEM0:r:q:i64
XED_ADCX_GPR64i64_MEMi64_APX
REG0=GPR64_R():rw:q:i64 MEM0:r:q:i64
XED_ADCX_X86_LEGACY_0F38_F6_717703
REG0=GPR32_R():rw:d REG1=GPR32_B():r:d REG0=GPR32_R():rw:d MEM0:r:d REG0=GPR64_R():rw:q REG1=GPR64_B():r:q REG0=GPR64_R():rw:q MEM0:r:q