AND
LOGICAL APX_F x86_64
AND is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category LOGICAL. This page lists its 53 encoding forms, distinguished by opcode bytes: 20, 21, 22, 23, 24, 25, 80, 81 and 2 more.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_AND_X86_LEGACY_ONEBYTE_81_29543
r16/m16, imm16
XED_AND_GPR8_GPR8_20
REG0=GPR8_B():rw REG1=GPR8_R():r
XED_AND_GPR8_GPR8_22
REG0=GPR8_R():rw REG1=GPR8_B():r REG0=GPR8_R():rw MEM0:r:b
XED_AND_GPR8i8_GPR8i8_APX
REG0=GPR8_B():rw:b:i8 REG1=GPR8_R():r:b:i8
XED_AND_GPR8i8_GPR8i8_APX_N3
REG0=GPR8_B():rw:b:i8 REG1=GPR8_R():r:b:i8
XED_AND_GPR8i8_GPR8i8_GPR8i8_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_B():r:b:i8 REG2=GPR8_R():r:b:i8
XED_AND_GPR8i8_GPR8i8_IMM8_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_B():r:b:i8 IMM0:r:b:i8
XED_AND_GPR8i8_GPR8i8_MEMi8_APX_N3
REG0=GPR8_N():w:b:i8 REG1=GPR8_R():r:b:i8 MEM0:r:b:i8
XED_AND_GPR8i8_IMM8_APX
REG0=GPR8_B():rw:b:i8 IMM0:r:b:i8
XED_AND_GPR8i8_IMM8_APX_N3
REG0=GPR8_B():rw:b:i8 IMM0:r:b:i8
XED_AND_GPR8i8_MEMi8_APX
REG0=GPR8_R():rw:b:i8 MEM0:r:b:i8
XED_AND_GPR8i8_MEMi8_APX_N3
REG0=GPR8_R():rw:b:i8 MEM0:r:b:i8
XED_AND_GPR8i8_MEMi8_GPR8i8_APX_N3
REG0=GPR8_N():w:b:i8 MEM0:r:b:i8 REG1=GPR8_R():r:b:i8
XED_AND_GPR8i8_MEMi8_IMM8_APX_N3
REG0=GPR8_N():w:b:i8 MEM0:r:b:i8 IMM0:r:b:i8
XED_AND_GPR8_IMMb_80r4
REG0=GPR8_B():rw IMM0:r:b
XED_AND_GPR8_IMMb_82r4
REG0=GPR8_B():rw IMM0:r:b
XED_AND_GPRv_GPRv_21
REG0=GPRv_B():rw REG1=GPRv_R():r
XED_AND_GPRv_GPRv_23
REG0=GPRv_R():rw REG1=GPRv_B():r REG0=GPRv_R():rw MEM0:r:v
XED_AND_GPRv_GPRv_APX
REG0=GPRv_B():rw:v REG1=GPRv_R():r:v
XED_AND_GPRv_GPRv_APX_N3
REG0=GPRv_B():rw:v REG1=GPRv_R():r:v
XED_AND_GPRv_GPRv_GPRv_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v REG2=GPRv_R():r:v
XED_AND_GPRv_GPRv_IMM8_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v IMM0:r:b:i8
XED_AND_GPRv_GPRv_IMMz_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v IMM0:r:z
XED_AND_GPRv_GPRv_MEMv_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_R():r:v MEM0:r:v
XED_AND_GPRv_IMM8_APX
REG0=GPRv_B():rw:v IMM0:r:b:i8
XED_AND_GPRv_IMM8_APX_N3
REG0=GPRv_B():rw:v IMM0:r:b:i8
XED_AND_GPRv_IMMz_APX
REG0=GPRv_B():rw:v IMM0:r:z
XED_AND_GPRv_IMMz_APX_N3
REG0=GPRv_B():rw:v IMM0:r:z
XED_AND_GPRv_MEMv_APX
REG0=GPRv_R():rw:v MEM0:r:v
XED_AND_GPRv_MEMv_APX_N3
REG0=GPRv_R():rw:v MEM0:r:v
XED_AND_GPRv_MEMv_GPRv_APX_N3
REG0=GPRv_N():w:v MEM0:r:v REG1=GPRv_R():r:v
XED_AND_GPRv_MEMv_IMM8_APX_N3
REG0=GPRv_N():w:v MEM0:r:v IMM0:r:b:i8
XED_AND_GPRv_MEMv_IMMz_APX_N3
REG0=GPRv_N():w:v MEM0:r:v IMM0:r:z
XED_AND_MEMb_IMMb_80r4
MEM0:rw:b IMM0:r:b
XED_AND_MEMb_IMMb_82r4
MEM0:rw:b IMM0:r:b
XED_AND_MEMi8_GPR8i8_APX
MEM0:rw:b:i8 REG0=GPR8_R():r:b:i8
XED_AND_MEMi8_GPR8i8_APX_N3
MEM0:rw:b:i8 REG0=GPR8_R():r:b:i8
XED_AND_MEMi8_IMM8_APX
MEM0:rw:b:i8 IMM0:r:b:i8
XED_AND_MEMi8_IMM8_APX_N3
MEM0:rw:b:i8 IMM0:r:b:i8
XED_AND_MEMv_GPRv_APX
MEM0:rw:v REG0=GPRv_R():r:v
XED_AND_MEMv_GPRv_APX_N3
MEM0:rw:v REG0=GPRv_R():r:v
XED_AND_MEMv_IMM8_APX
MEM0:rw:v IMM0:r:b:i8
XED_AND_MEMv_IMM8_APX_N3
MEM0:rw:v IMM0:r:b:i8
XED_AND_MEMv_IMMz_APX
MEM0:rw:v IMM0:r:z
XED_AND_MEMv_IMMz_APX_N3
MEM0:rw:v IMM0:r:z
XED_AND_X86_LEGACY_ONEBYTE_20_403135
MEM0:rw:b REG0=GPR8_R():r
XED_AND_X86_LEGACY_ONEBYTE_21_606246
MEM0:rw:v REG0=GPRv_R():r
XED_AND_X86_LEGACY_ONEBYTE_24_891504
REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8
XED_AND_X86_LEGACY_ONEBYTE_25_83611
REG0=OrAX():rw:IMPL IMM0:r:z
XED_AND_X86_LEGACY_ONEBYTE_81_29880
MEM0:rw:v IMM0:r:z
XED_AND_X86_LEGACY_ONEBYTE_81_835105
REG0=GPRv_B():rw IMM0:r:z
XED_AND_X86_LEGACY_ONEBYTE_83_564997
REG0=GPRv_B():rw IMM0:r:b:i8
XED_AND_X86_LEGACY_ONEBYTE_83_717852
MEM0:rw:v IMM0:r:b:i8