FXCH

X87_ALU X87 x86_64

FXCH is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category X87_ALU. This page lists its 4 encoding forms, distinguished by opcode bytes: D9, DD, DF.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

X86_FXCH_X86_LEGACY_ONEBYTE_D9_0
(no syntax)
X86_LEGACY D9 FPU
X86_FXCH_X86_LEGACY_ONEBYTE_D9_10310
st(i)
X86_LEGACY D9 FPU
XED_FXCH_ST0_X87_DFC1 FXCH_ST0_X87_DDC1
REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP
X86_LEGACY DF DD /1 X87
XED_FXCH_X86_LEGACY_ONEBYTE_D9_714948
REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP
X86_LEGACY D9 /1 X87