FXCH
REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP
x86_64 X86_LEGACY X87_ALU X87 source: xed
XED_FXCH_ST0_X87_DFC1 FXCH_ST0_X87_DDC1
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | DF DD |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| modrm.reg = /1 | /1 |
| attributes | NOTSX UNDOCUMENTED |
| cpl | 3 |
| raw_encoding | 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn] 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn] |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | (=ST0) | f80 | RW | IMPLICIT | MODRM_REG |
| 1 | REG1 | REG | f80 | RW | EXPLICIT | MODRM_REG | |
| 2 | REG2 | REG | w | W | SUPPRESSED | MODRM_REG | |
| 3 | REG3 | REG | (=ST0) | f80 | RW | IMPLICIT | MODRM_REG |
| 4 | REG4 | REG | f80 | RW | EXPLICIT | MODRM_REG | |
| 5 | REG5 | REG | w | W | SUPPRESSED | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.