NOP

WIDENOP PPRO x86_64

NOP is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category WIDENOP. This page lists its 17 encoding forms, distinguished by opcode bytes: 00, 0F, 18, 19, 1A, 1B, 1C, 1D and 3 more.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

X86_NOP_X86_LEGACY_0F_1F_352768
rv/mv
X86_LEGACY 1F /0
X86_NOP_X86_LEGACY_0F_1F_602567
rv/mv, rv
X86_LEGACY 1F /r
X86_NOP_X86_LEGACY_ONEBYTE_90_0
(no syntax)
X86_LEGACY 90
XED_NOP_90
(no syntax)
X86_LEGACY 00 I86
XED_NOP_GPRv_0F18r0 NOP_GPRv_0F18r1 NOP_GPRv_0F18r2 NOP_GPRv_0F18r3 NOP_GPRv_0F18r4 NOP_MEMv_0F18r5 NOP_GPRv_0F18r5 NOP_GPRv_0F18r6 NOP_GPRv_0F18r7
REG0=GPRv_B():r REG0=GPRv_B():r REG0=GPRv_B():r REG0=GPRv_B():r REG0=GPRv_B():r MEM0:r:v REG0=GPRv_B():r REG0=GPRv_B():r REG0=GPRv_B():r
X86_LEGACY 18 0F 18 0F 18 0F 18 0F 18 0F 18 0F 18 0F 18 0F 18 /7 FAT_NOP
XED_NOP_GPRv_GPRv_0F1A NOP_GPRv_GPRv_0F1B NOP_GPRv_GPRv_0F1B
REG0=GPRv_B():r REG1=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r
X86_LEGACY 1A 0F 1B 0F 1B /r PPRO
XED_NOP_GPRv_GPRv_0F1A NOP_GPRv_GPRv_0F1B NOP_GPRv_MEMv_0F1A NOP_GPRv_MEM_0F1B
REG0=GPRv_B():r REG1=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r REG0=GPRv_B():r MEM0:r:v REG0=GPRv_B():r MEM0:r:v
X86_LEGACY 1A 0F 1B 0F 1A 0F 1B /r PPRO
XED_NOP_MEMv_0F18r4
MEM0:r:v
X86_LEGACY 18 /4 FAT_NOP
XED_NOP_MEMv_0F18r6
MEM0:r:v
X86_LEGACY 18 /6 FAT_NOP
XED_NOP_MEMv_0F18r7
MEM0:r:v
X86_LEGACY 18 /7 FAT_NOP
XED_NOP_MEMv_0F1F NOP_GPRv_0F1F
MEM0:r:v REG0=GPRv_B():r
X86_LEGACY 1F 0F 1F /r FAT_NOP
XED_NOP_MEMv_GPRv_0F19 NOP_GPRv_GPRv_0F19
MEM0:r:v REG0=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r
X86_LEGACY 19 0F 19 /r FAT_NOP
XED_NOP_MEMv_GPRv_0F1A NOP_GPRv_GPRv_0F1A
MEM0:r:v REG0=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r
X86_LEGACY 1A 0F 1A /r FAT_NOP
XED_NOP_MEMv_GPRv_0F1B NOP_GPRv_GPRv_0F1B
MEM0:r:v REG0=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r
X86_LEGACY 1B 0F 1B /r FAT_NOP
XED_NOP_MEMv_GPRv_0F1C NOP_GPRv_GPRv_0F1C
MEM0:r:v REG0=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r
X86_LEGACY 1C 0F 1C /r FAT_NOP
XED_NOP_MEMv_GPRv_0F1D NOP_GPRv_GPRv_0F1D
MEM0:r:v REG0=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r
X86_LEGACY 1D 0F 1D /r FAT_NOP
XED_NOP_MEMv_GPRv_0F1E NOP_GPRv_GPRv_0F1E
MEM0:r:v REG0=GPRv_R():r REG0=GPRv_B():r REG1=GPRv_R():r
X86_LEGACY 1E 0F 1E /r FAT_NOP