PINSRW

MMX PENTIUMMMX x86_64

PINSRW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category MMX. This page lists its 4 encoding forms, distinguished by opcode bytes: 0F, C4.

Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.

X86_PINSRW_X86_LEGACY_0F_C4_488559

mm, r32[15:0]/m16, imm8

X86_LEGACY C4 /r MMX2

X86_PINSRW_X86_LEGACY_0F_C4_574680

xmm, r32[15:0]/m16, imm8

X86_LEGACY C4 /r SSE2

XED_PINSRW_X86_LEGACY_0F_C4_861373

REG0=MMX_R():rw:q:u16 MEM0:r:w:u16 IMM0:r:b REG0=MMX_R():rw:q:u16 REG1=GPR32_B():r IMM0:r:b

X86_LEGACY C4 0F C4 /r PENTIUMMMX

XED_PINSRW_X86_LEGACY_0F_C4_945926

REG0=XMM_R():rw:dq MEM0:r:w IMM0:r:b REG0=XMM_R():rw:dq REG1=GPR32_B():r IMM0:r:b

X86_LEGACY C4 0F C4 /r SSE2