SHLD
REG0=GPRv_B():rcw:v REG1=GPRv_R():r:v IMM0:r:b
x86_64 X86_LEGACY SHIFT APX_F source: xed
XED_SHLD_GPRv_GPRv_IMM8_APX
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 24 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| imm_size_bytes | 1 |
| requires_mode | long |
| exception_class | APX-EVEX-INT |
| cpl | 3 |
| raw_encoding | EVV 0x24 VNP MAP4 MOD[0b11] MOD=3 UBIT=1 REG[rrr] RM[nnn] ND=0 NF=0 VL128 mode64 NOEVSR ZEROING=0 EVAPX() UIMM8() |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | v | R | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | v | R | EXPLICIT | MODRM_REG | |
| 2 | IMM0 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.