SHLD
SHIFT APX_F x86_64
16 encoding forms.
X86_SHLD_X86_LEGACY_0F_A4_638652
rv/mv, rv, imm8
X86_SHLD_X86_LEGACY_0F_A5_21359
rv/mv, rv, cl
XED_SHLD_GPRv_GPRv_CL_APX
REG0=GPRv_B():rcw:v REG1=GPRv_R():r:v REG2=XED_REG_CL:r:IMPL
XED_SHLD_GPRv_GPRv_CL_APX_N3
REG0=GPRv_B():rcw:v REG1=GPRv_R():r:v REG2=XED_REG_CL:r:IMPL
XED_SHLD_GPRv_GPRv_GPRv_CL_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v REG2=GPRv_R():r:v REG3=XED_REG_CL:r:IMPL
XED_SHLD_GPRv_GPRv_GPRv_IMM8_APX_N3
REG0=GPRv_N():w:v REG1=GPRv_B():r:v REG2=GPRv_R():r:v IMM0:r:b
XED_SHLD_GPRv_GPRv_IMM8_APX
REG0=GPRv_B():rcw:v REG1=GPRv_R():r:v IMM0:r:b
XED_SHLD_GPRv_GPRv_IMM8_APX_N3
REG0=GPRv_B():rcw:v REG1=GPRv_R():r:v IMM0:r:b
XED_SHLD_GPRv_MEMv_GPRv_CL_APX_N3
REG0=GPRv_N():w:v MEM0:r:v REG1=GPRv_R():r:v REG2=XED_REG_CL:r:IMPL
XED_SHLD_GPRv_MEMv_GPRv_IMM8_APX_N3
REG0=GPRv_N():w:v MEM0:r:v REG1=GPRv_R():r:v IMM0:r:b
XED_SHLD_MEMv_GPRv_CL_APX
MEM0:rcw:v REG0=GPRv_R():r:v REG1=XED_REG_CL:r:IMPL
XED_SHLD_MEMv_GPRv_CL_APX_N3
MEM0:rcw:v REG0=GPRv_R():r:v REG1=XED_REG_CL:r:IMPL
XED_SHLD_MEMv_GPRv_IMM8_APX
MEM0:rcw:v REG0=GPRv_R():r:v IMM0:r:b
XED_SHLD_MEMv_GPRv_IMM8_APX_N3
MEM0:rcw:v REG0=GPRv_R():r:v IMM0:r:b
XED_SHLD_X86_LEGACY_0F_A4_197171
MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b
XED_SHLD_X86_LEGACY_0F_A5_343613
MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL