SHLD
MEM0:rcw:v REG0=GPRv_R():r:v REG1=XED_REG_CL:r:IMPL
x86_64 X86_LEGACY SHIFT APX_F_N3 source: xed
XED_SHLD_MEMv_GPRv_CL_APX_N3
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | A5 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| requires_mode | long |
| attributes | APX_NF DISP8_NO_SCALE |
| exception_class | APX-EVEX-INT |
| cpl | 3 |
| raw_encoding | EVV 0xA5 VNP MAP4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() ND=0 NF=1 VL128 mode64 NOEVSR ZEROING=0 EVAPX() |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | v | R | EXPLICIT | MODRM_RM | |
| 1 | REG0 | REG | v | R | EXPLICIT | MODRM_REG | |
| 2 | REG1 | REG | (=CL) | R | IMPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.