VCVTPH2PS
CONVERT AVX512F_128 x86_64
VCVTPH2PS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 7 encoding forms, distinguished by opcode byte: 13.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTPH2PS_X86_LEGACY_ONEBYTE_13_172989
REG0=XMM_R():w:dq:f32 MEM0:r:q:f16 REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:q:f16 REG0=YMM_R():w:qq:f32 MEM0:r:dq:f16 REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f16
XED_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16
XED_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512
REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
XED_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16
XED_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512
REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16
XED_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16
XED_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512
REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16