VCVTSD2SI
CONVERT AVX512F_SCALAR x86_64
VCVTSD2SI is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 5 encoding forms, distinguished by opcode byte: 2D.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTSD2SI_GPR32i32_MEMf64_AVX512 VCVTSD2SI_GPR32i32_MEMf64_AVX512
REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 REG0=GPR32_R():w:d:i32 MEM0:r:q:f64
XED_VCVTSD2SI_GPR32i32_XMMf64_AVX512 VCVTSD2SI_GPR32i32_XMMf64_AVX512
REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64
XED_VCVTSD2SI_GPR64i64_MEMf64_AVX512
REG0=GPR64_R():w:q:i64 MEM0:r:q:f64
XED_VCVTSD2SI_GPR64i64_XMMf64_AVX512
REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64
XED_VCVTSD2SI_X86_LEGACY_ONEBYTE_2D_57713
REG0=VGPR32_R():w:d:i32 MEM0:r:q:f64 REG0=VGPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 REG0=VGPR32_R():w:d:i32 MEM0:r:q:f64 REG0=VGPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 REG0=VGPR64_R():w:q:i64 MEM0:r:q:f64 REG0=VGPR64_R():w:q:i64 REG1=XMM_B():r:q:f64