VCVTSI2SS
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
x86_64 X86_LEGACY CONVERT AVX512F_SCALAR source: xed
XED_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 2A 2A |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| requires_mode | long |
| attributes | MXCSR SIMD_SCALAR |
| exception_class | AVX512-E3NF |
| cpl | 3 |
| raw_encoding | EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 2 | REG2 | REG | d | R | EXPLICIT | MODRM_REG | |
| 3 | REG3 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | REG4 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 5 | REG5 | REG | d | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.