VCVTSI2SS
CONVERT AVX512F_SCALAR x86_64
VCVTSI2SS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 5 encoding forms, distinguished by opcode byte: 2A.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTSI2SS_X86_LEGACY_ONEBYTE_2A_884452
REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=VGPR32_B():r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=VGPR32_B():r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=VGPR64_B():r:q:i64
XED_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32
XED_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64
XED_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32
XED_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64