VCVTSI2SS

REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=VGPR32_B():r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=VGPR32_B():r:d:i32 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64 REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=VGPR64_B():r:q:i64

x86_64 X86_LEGACY CONVERT AVX source: xed

XED_VCVTSI2SS_X86_LEGACY_ONEBYTE_2A_884452

Encoding

encoding_kindX86_LEGACY
opcode_bytes2A 2A 2A 2A 2A 2A
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
rex_w1
requires_modelong
attributessimd_scalar MXCSR
exception_classavx-type-3
cpl3
raw_encodingVV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]

Operands (18)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG f32 R EXPLICIT MODRM_REG
2 MEM0 MEM d R EXPLICIT MODRM_RM
3 REG2 REG w W EXPLICIT MODRM_REG
4 REG3 REG f32 R EXPLICIT MODRM_REG
5 REG4 REG d R EXPLICIT MODRM_REG
6 REG5 REG w W EXPLICIT MODRM_REG
7 REG6 REG f32 R EXPLICIT MODRM_REG
8 MEM1 MEM d R EXPLICIT MODRM_RM
9 REG7 REG w W EXPLICIT MODRM_REG
10 REG8 REG f32 R EXPLICIT MODRM_REG
11 REG9 REG d R EXPLICIT MODRM_REG
12 REG10 REG w W EXPLICIT MODRM_REG
13 REG11 REG f32 R EXPLICIT MODRM_REG
14 MEM2 MEM q R EXPLICIT MODRM_RM
15 REG12 REG w W EXPLICIT MODRM_REG
16 REG13 REG f32 R EXPLICIT MODRM_REG
17 REG14 REG q R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.