VCVTTPD2UDQS
CONVERT AVX512_SAT_CVT_DS_128 x86_64
VCVTTPD2UDQS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 6 encoding forms, distinguished by opcode byte: 6C.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL128
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
XED_VCVTTPD2UDQS_XMMu32_MASKmskw_MEMf64_AVX512_VL256
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
XED_VCVTTPD2UDQS_XMMu32_MASKmskw_XMMf64_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
XED_VCVTTPD2UDQS_XMMu32_MASKmskw_YMMf64_AVX512
REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
XED_VCVTTPD2UDQS_YMMu32_MASKmskw_MEMf64_AVX512_VL512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
XED_VCVTTPD2UDQS_YMMu32_MASKmskw_ZMMf64_AVX512
REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64