VCVTUSI2SS
CONVERT AVX512F_SCALAR x86_64
VCVTUSI2SS is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category CONVERT. This page lists its 4 encoding forms, distinguished by opcode byte: 7B.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32
XED_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64
XED_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32
XED_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512
REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64