VEXTRACTI64X2
AVX512 AVX512DQ_256 x86_64
VEXTRACTI64X2 is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 4 encoding forms, distinguished by opcode byte: 39.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512
MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b
XED_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512
MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b
XED_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512
REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b
XED_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512
REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b