VEXTRACTI64X2
MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b
x86_64 X86_LEGACY AVX512 AVX512DQ_256 source: xed
XED_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 39 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 1 |
| imm_size_bytes | 1 |
| attributes | DISP8_TUPLE2 MASKOP_EVEX |
| exception_class | AVX512-E6NF |
| cpl | 3 |
| raw_encoding | EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 UBIT=1 W1 VL256 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | w | W | EXPLICIT | MODRM_RM | |
| 1 | REG0 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 3 | IMM0 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.