VEXTRACTPS
MEM0:w:d:f32 REG0=XMM_R():r:dq:f32 IMM0:r:b REG0=VGPR32_B():w REG1=XMM_R():r:dq:f32 IMM0:r:b
x86_64 X86_LEGACY AVX512 AVX source: xed
XED_VEXTRACTPS_X86_LEGACY_ONEBYTE_17_267186
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 17 17 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| imm_size_bytes | 1 |
| exception_class | avx-type-5 |
| cpl | 3 |
| raw_encoding | VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | MEM0 | MEM | w | W | EXPLICIT | MODRM_RM | |
| 1 | REG0 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 2 | IMM0 | IMM | b | R | EXPLICIT | IMM | |
| 3 | REG1 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | REG2 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 5 | IMM1 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.