VMOVAPD
DATAXFER AVX512F_128 x86_64
10 encoding forms.
XED_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512
MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64
XED_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512
MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64
XED_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512
MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64
XED_VMOVAPD_XMMdq_XMMdq_28 VMOVAPD_XMMdq_XMMdq_29 VMOVAPD_YMMqq_YMMqq_28 VMOVAPD_YMMqq_YMMqq_29
REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64
XED_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64
XED_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512
REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64
XED_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64
XED_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512
REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64
XED_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64
XED_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512
REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64