VMOVQ
DATAXFER AVX512F_128N x86_64
VMOVQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 9 encoding forms, distinguished by opcode bytes: 6E, 7E, D6.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VMOVQ_GPR64u64_XMMu64_AVX512
REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64
XED_VMOVQ_MEMq_XMMq_7E VMOVQ_XMMdq_MEMq_7E
MEM0:w:q REG0=XMM_R():r:q REG0=XMM_R():w:dq MEM0:r:q
XED_VMOVQ_MEMq_XMMq_D6
MEM0:w:q REG0=XMM_R():r:q
XED_VMOVQ_MEMu64_XMMu64_AVX512
MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64
XED_VMOVQ_XMMdq_MEMq_6E
REG0=XMM_R():w:dq MEM0:r:q
XED_VMOVQ_XMMdq_XMMq_7E VMOVQ_XMMdq_XMMq_D6
REG0=XMM_R():w:dq REG1=VGPR64_B():r:q REG0=VGPR64_B():w:q REG1=XMM_R():r:q REG0=XMM_R():w:dq REG1=XMM_B():r:q REG0=XMM_B():w:dq REG1=XMM_R():r:q
XED_VMOVQ_XMMu64_GPR64u64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64
XED_VMOVQ_XMMu64_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64
XED_VMOVQ_XMMu64_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64