VMOVQ
REG0=XMM_R():w:dq REG1=VGPR64_B():r:q REG0=VGPR64_B():w:q REG1=XMM_R():r:q REG0=XMM_R():w:dq REG1=XMM_B():r:q REG0=XMM_B():w:dq REG1=XMM_R():r:q
x86_64 X86_LEGACY DATAXFER AVX source: xed
XED_VMOVQ_XMMdq_XMMq_7E VMOVQ_XMMdq_XMMq_D6
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 6E 7E 7E D6 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| rex_w | 1 |
| vex_l | 0 |
| requires_mode | long |
| exception_class | avx-type-5 |
| cpl | 3 |
| raw_encoding | VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] |
Operands (8)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | q | R | EXPLICIT | MODRM_REG | |
| 2 | REG2 | REG | w | W | EXPLICIT | MODRM_REG | |
| 3 | REG3 | REG | q | R | EXPLICIT | MODRM_REG | |
| 4 | REG4 | REG | w | W | EXPLICIT | MODRM_REG | |
| 5 | REG5 | REG | q | R | EXPLICIT | MODRM_REG | |
| 6 | REG6 | REG | w | W | EXPLICIT | MODRM_REG | |
| 7 | REG7 | REG | q | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.