VMOVSS
REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 REG0=XMM_B():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_R():r:d:f32
x86_64 X86_LEGACY DATAXFER AVX source: xed
XED_VMOVSS_XMMdq_XMMdq_XMMd_10 VMOVSS_XMMdq_XMMdq_XMMd_11
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 10 11 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| attributes | simd_scalar |
| exception_class | avx-type-5 |
| cpl | 3 |
| raw_encoding | VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] |
Operands (6)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 2 | REG2 | REG | d | R | EXPLICIT | MODRM_REG | |
| 3 | REG3 | REG | w | W | EXPLICIT | MODRM_REG | |
| 4 | REG4 | REG | f32 | R | EXPLICIT | MODRM_REG | |
| 5 | REG5 | REG | d | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.