VP2INTERSECTQ
AVX512_VP2INTERSECT AVX512_VP2INTERSECT_128 x86_64
VP2INTERSECTQ is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512_VP2INTERSECT. This page lists its 6 encoding forms, distinguished by opcode byte: 68.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
XED_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64
XED_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
XED_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64
XED_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
XED_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64