VP2INTERSECTQ
REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64
x86_64 X86_LEGACY AVX512_VP2INTERSECT AVX512_VP2INTERSECT_128 source: xed
XED_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 68 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 0 |
| attributes | MULTIDEST2 |
| exception_class | AVX512-E4 |
| cpl | 3 |
| raw_encoding | EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 MASK=0 |
Operands (3)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | R | EXPLICIT | MODRM_REG |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.