VPCLMULQDQ
AVX AVX x86_64
9 encoding forms.
XED_VPCLMULQDQ_X86_LEGACY_ONEBYTE_44_488759
REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b
XED_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512
REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b
XED_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512
REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b
XED_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8
REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b
XED_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512
REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b
XED_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8
REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 IMM0:r:b
XED_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512
REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b
XED_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512
REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b
XED_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512
REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b