VPCLMULQDQ

REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b

x86_64 X86_LEGACY AVX AVX source: xed

XED_VPCLMULQDQ_X86_LEGACY_ONEBYTE_44_488759

Encoding

encoding_kindX86_LEGACY
opcode_bytes44 44
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l0
imm_size_bytes1
exception_classavx-type-4
cpl3
raw_encodingVV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8() VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8()

Operands (8)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG R EXPLICIT MODRM_REG
2 REG2 REG R EXPLICIT MODRM_REG
3 IMM0 IMM b R EXPLICIT IMM
4 REG3 REG w W EXPLICIT MODRM_REG
5 REG4 REG R EXPLICIT MODRM_REG
6 MEM0 MEM R EXPLICIT MODRM_RM
7 IMM1 IMM b R EXPLICIT IMM

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.