VPCMOV
XOP XOP x86_64
VPCMOV is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category XOP. This page lists its 5 encoding forms, distinguished by opcode byte: A2.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
X86_VPCMOV_X86_LEGACY_ONEBYTE_A2_116380
ymm, ymm, ymm/m256, ymm
X86_VPCMOV_X86_LEGACY_ONEBYTE_A2_624972
xmm, xmm, xmm, xmm/m128
X86_VPCMOV_X86_LEGACY_ONEBYTE_A2_642564
ymm, ymm, ymm, ymm/m256
X86_VPCMOV_X86_LEGACY_ONEBYTE_A2_714560
xmm, xmm, xmm/m128, xmm
XED_VPCMOV_X86_LEGACY_ONEBYTE_A2_309271
REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1 REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1 REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1 REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1