VPCMOV

REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1 REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1 REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1 REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1 REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1

x86_64 X86_LEGACY XOP XOP source: xed

XED_VPCMOV_X86_LEGACY_ONEBYTE_A2_309271

Encoding

encoding_kindX86_LEGACY
opcode_bytesA2 A2 A2 A2 A2 A2 A2 A2
opcode_mapONEBYTE
mandatory_prefix-
has_modrmTrue
vex_l1
attributesAMDONLY
cpl3
raw_encodingXOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()

Operands (32)

# Role Kind Class / Reg Width Access Visibility Encoded in
0 REG0 REG w W EXPLICIT MODRM_REG
1 REG1 REG R EXPLICIT MODRM_REG
2 MEM0 MEM R EXPLICIT MODRM_RM
3 REG2 REG R EXPLICIT MODRM_REG
4 REG3 REG w W EXPLICIT MODRM_REG
5 REG4 REG R EXPLICIT MODRM_REG
6 REG5 REG R EXPLICIT MODRM_REG
7 REG6 REG R EXPLICIT MODRM_REG
8 REG7 REG w W EXPLICIT MODRM_REG
9 REG8 REG R EXPLICIT MODRM_REG
10 REG9 REG R EXPLICIT MODRM_REG
11 MEM1 MEM R EXPLICIT MODRM_RM
12 REG10 REG w W EXPLICIT MODRM_REG
13 REG11 REG R EXPLICIT MODRM_REG
14 REG12 REG R EXPLICIT MODRM_REG
15 REG13 REG R EXPLICIT MODRM_REG
16 REG14 REG w W EXPLICIT MODRM_REG
17 REG15 REG R EXPLICIT MODRM_REG
18 MEM2 MEM R EXPLICIT MODRM_RM
19 REG16 REG R EXPLICIT MODRM_REG
20 REG17 REG w W EXPLICIT MODRM_REG
21 REG18 REG R EXPLICIT MODRM_REG
22 REG19 REG R EXPLICIT MODRM_REG
23 REG20 REG R EXPLICIT MODRM_REG
24 REG21 REG w W EXPLICIT MODRM_REG
25 REG22 REG R EXPLICIT MODRM_REG
26 REG23 REG R EXPLICIT MODRM_REG
27 MEM3 MEM R EXPLICIT MODRM_RM
28 REG24 REG w W EXPLICIT MODRM_REG
29 REG25 REG R EXPLICIT MODRM_REG
30 REG26 REG R EXPLICIT MODRM_REG
31 REG27 REG R EXPLICIT MODRM_REG

Micro-ops sequence (0)

No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.