VPCMPEQW
AVX512 AVX512BW_128 x86_64
VPCMPEQW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category AVX512. This page lists its 8 encoding forms, distinguished by opcode byte: 75.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
XED_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
XED_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
XED_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
XED_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
XED_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16
XED_VPCMPEQW_X86_LEGACY_ONEBYTE_75_697020
REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16
XED_VPCMPEQW_X86_LEGACY_ONEBYTE_75_914790
REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16