VPMADD52HUQ
AVX_IFMA AVX_IFMA x86_64
10 encoding forms.
XED_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
XED_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
XED_VPMADD52HUQ_XMMu64_XMMu64_MEMu64
REG0=XMM_R():rw:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64
XED_VPMADD52HUQ_XMMu64_XMMu64_XMMu64
REG0=XMM_R():rw:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
XED_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
XED_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512
REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64
XED_VPMADD52HUQ_YMMu64_YMMu64_MEMu64
REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64
XED_VPMADD52HUQ_YMMu64_YMMu64_YMMu64
REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64
XED_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR
XED_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512
REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64