VPMADD52HUQ
REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR
x86_64 X86_LEGACY AVX_IFMA AVX512_IFMA_256 source: xed
XED_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | B5 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| vex_l | 1 |
| attributes | MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED |
| exception_class | AVX512-E4 |
| cpl | 3 |
| raw_encoding | EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 UBIT=1 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | RW | EXPLICIT | MODRM_REG | ||
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | REG2 | REG | R | EXPLICIT | MODRM_REG | ||
| 3 | MEM0 | MEM | R | EXPLICIT | MODRM_RM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.