VPMOVZXWD
DATAXFER AVX512F_128 x86_64
VPMOVZXWD is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category DATAXFER. This page lists its 8 encoding forms, distinguished by opcode byte: 33.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPMOVZXWD_X86_LEGACY_ONEBYTE_33_763313
REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 REG0=XMM_R():w:dq:u32 MEM0:r:q:u16
XED_VPMOVZXWD_X86_LEGACY_ONEBYTE_33_806662
REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16
XED_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16
XED_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512
REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
XED_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512
REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16
XED_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512
REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16
XED_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512
REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16
XED_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512
REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16