VPSLLW
REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b
x86_64 X86_LEGACY AVX512 AVX512BW_128 source: xed
XED_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512
Encoding
| encoding_kind | X86_LEGACY |
| opcode_bytes | 71 |
| opcode_map | ONEBYTE |
| mandatory_prefix | - |
| has_modrm | True |
| modrm.reg = /6 | /6 |
| vex_l | 0 |
| imm_size_bytes | 1 |
| attributes | DISP8_FULLMEM MASKOP_EVEX MEMORY_FAULT_SUPPRESSION |
| exception_class | AVX512-E4 |
| cpl | 3 |
| raw_encoding | EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() BCRC=0 UBIT=1 VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() |
Operands (4)
| # | Role | Kind | Class / Reg | Width | Access | Visibility | Encoded in |
|---|---|---|---|---|---|---|---|
| 0 | REG0 | REG | w | W | EXPLICIT | MODRM_REG | |
| 1 | REG1 | REG | R | EXPLICIT | MODRM_REG | ||
| 2 | MEM0 | MEM | R | EXPLICIT | MODRM_RM | ||
| 3 | IMM0 | IMM | b | R | EXPLICIT | IMM |
Micro-ops sequence (0)
No micro-ops authored for this encoding. Emulator semantics not yet defined — decoder still works.