VPSRLQ
AVX512 AVX512F_128 x86_64
16 encoding forms.
XED_VPSRLQ_X86_LEGACY_ONEBYTE_73_748481
REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b
XED_VPSRLQ_X86_LEGACY_ONEBYTE_73_955958
REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b
XED_VPSRLQ_X86_LEGACY_ONEBYTE_D3_530234
REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64
XED_VPSRLQ_X86_LEGACY_ONEBYTE_D3_875548
REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64
XED_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512
REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
XED_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512
REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b
XED_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64
XED_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512
REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64
XED_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512
REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
XED_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512
REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b
XED_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64
XED_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512
REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64
XED_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512
REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b
XED_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512
REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b
XED_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64
XED_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512
REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64