VPTESTNMW
LOGICAL AVX512BW_128 x86_64
VPTESTNMW is an instruction of the x86_64 architecture (x86 / x86-64 (covers 16/32/64-bit modes)), category LOGICAL. This page lists its 6 encoding forms, distinguished by opcode byte: 26.
Each form below links to its full decode: the operand roles and where each one is encoded in the instruction, the flag and register effects, and any micro-op sequence authored for it.
XED_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16
XED_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16
XED_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16
XED_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16
XED_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16
XED_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512
REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16